With all the hype surrounding competing verification methodologies, it’s time for a cool head and to prove that you can indeed teach an old dog new tricks
For the last 20 years I have worked as a hardware engineer, having held senior and principal engineering roles at several large companies. More recently however, I have taken the opportunity to ‘jump the fence’ from engineering into the world of EDA. Even though I will effectively be working in the same industry, I am looking forward to experiencing it from a new perspective. I am sure that my past experiences will stand me in good stead, providing the base knowledge and experience required to effectively support customers, but I am always willing to learn new things.
FirstEDA are the local distributor for several established EDA companies, as well as offering language and methodology training. As part of my introduction to the company, I was given the opportunity to attend our 5-day “Advanced VHDL Testbenches & Verification” training course. The objective was to strengthen my existing knowledge and skills as an engineer, to assist me in supporting our customers to the highest level.
Considering my previous job roles, you may find it surprising that this was the first time I have attended a training course of this type (a comment maybe on the attitude towards formal training in our industry?) and was therefore looking forward to establishing to what extent I might be able to improve my own knowledge of VHDL verification. Also to learn more about OSVVM in general, a VHDL based verification methodology that is increasingly popular amongst the customers that I will now be supporting. And who better to learn this from than Jim Lewis, the principle architect of OSVVM and Chair of the VHDL Standards Working Group at the IEEE.
The first thing to mention about my experience on this course, is how impressed I am with Jim Lewis. He is certainly very qualified to teach in this area. Jim is able to quickly grasp the individual requirements of each delegate and work with them to ensure that everyone progresses at their own pace. He certainly has the desire to teach too and is very passionate about VHDL verification. His knowledge and competence on the subject, his enthusiasm, motivation, ingenuity and creativity were all evident.
As billed, the course was certainly comprehensive but heavily practical based to ensure the knowledge stuck. The labs tracked the lectures, giving me the opportunity to exercise one of the many tools I will be supporting at FirstEDA, Aldec’s Riviera-PRO. I gained hands-on experience with the latest VHDL verification techniques using OSVVM, which I’m certain will be beneficial in understanding and supporting our customers. This methodology would also have no doubt benefitted me in my past engineering roles.
There was plenty of opportunity to talk to other delegates throughout the week and it is always interesting to find out how other companies are approaching their development activities. I found that most were primarily ASIC based but typically also worked on FPGA projects. One of the delegates told me that before the course he was setting up testbenches and reviewing the test results manually! So for him in particular, these new methods will be a great time saver. The overall picture I got from all delegates was that the course has improved their verification knowledge, particularly on how to structure and execute testing, but also that it acted as a very good refresher on how best to use the VHDL language. All delegates stated that they would recommend the course and were keen to start using their new-found knowledge on real projects to improve their verification flow.
My opinion is that our 5-day “Advanced VHDL Testbenches & Verification” course is ideal for FPGA/ASIC designers that are looking to improve their verification skills, learn more about good VHDL coding styles and how best to use the OSVVM packages in general. Despite the perceived push in our industry towards SystemVerilog, I learned that VHDL is far more capable than I had imagined. If you are already using VHDL for design, right now (fresh off the course) I’m struggling to see the benefit of moving to SystemVerilog for verification and would recommend careful consideration of all the options.
Our next 5-day Advanced Verification course (and the last public one of 2017!) is taking place in November (Bracknell, UK).