Live Webinar: Boost VHDL Development Time with Background Design Rule Checking - FirstEDA
22586
portfolio_page-template-default,single,single-portfolio_page,postid-22586,ajax_fade,page_not_loaded,,qode-child-theme-ver-1.0.0,qode-theme-ver-10.1.2,wpb-js-composer js-comp-ver-5.4.5,vc_responsive

Live Webinar: Boost VHDL Development Time with Background Design Rule Checking

Boost VHDL Development Time with Background Design Rule Checking

THURSDAY 30 NOVEMBER – 14:00-15:00 GMT (15:00-16:00 CET)

Presented by David Clift, FirstEDA Applications Specialist
& Hendrik Eeckhaut, Sigasi CTO

Design rule checking (DRC) is a battle-proven method to improve the quality of digital designs. In safety-critical design processes, such as DO-254, design rule checking tools are increasing deployed as the primary method to automate mandatory code reviews to achieve milestone sign-off. But why wait for this deadline before launching a DRC solution like ALINT-PRO to verify all design rules?

 

The longer it takes to find and fix an issue, the more expensive this gets, and nobody likes going through long lists of (potential) problems. Therefore, it is strongly recommended to run design rule checking regularly. But how do you manage this efficiently while creating your design?

 

Sigasi Studio is an IDE that makes HDL design easier and more efficient. Sigasi Studio can automatically run ALINT-PRO checks on your design files when you save your files. The checks run transparently in the background and the results are clearly presented right in the editor. This fast feedback enables you to fix the issues swiftly, and helps you focus on the important design challenges.

 

Agenda:

  • Why do Design Rule Checking?
  • Why wait till the next milestone?
  • Sigasi rapid code development methodology
  • Advanced rules in Aldec ALINT-PRO
  • Sign-off design rule checking
  • Demo
  • Summary
  • Q & A