FirstEDA press releases
FirstEDA are the Sales Channel for Aldec in the UK & Ireland
Laura Consoli Aldec, Inc. (702) 990-4400 ext. 214 laurac@aldec.com
Aldec Releases Active-HDL 7.1 with New Simulation Technology and SystemVerilog Support
Henderson, Nevada - October 31, 2005 -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Active-HDL 7.1. Active-HDL 7.1 is a new FPGA and ASIC design entry and verification platform with several new high productivity tools. New tools include, ultra-high speed gate-level simulation technology (SLP), VHDL and Verilog Linting tools, improved support for MATLABŪ and SimulinkŪ and new SystemVerilog simulation support.
Simulation Performance
Active-HDL 7.1 includes SLP simulation acceleration technology. The SLP technology uses a completely re-designed simulation engine that dramatically reduces simulation run times for Verilog gate-level and timing verification. SLP is transparent to the user and its employment requires zero effort. Simulation run times are also reduced for VHDL designs. Performance gains are most notable in timing simulations.
SystemVerilog
Active-HDL adds support for SystemVerilog, a set of extensions to Verilog HDL developed by Accellera. SystemVerilog brings usability improvements; it allows users to create more concise and clear code, in addition to modeling at more abstract levels. Active-HDL users can now embrace the benefits of this new technology.
GUI Improvements
The Design Flow Manager was updated to support the latest synthesis, place and route, and other vendor tools. Active-HDL continues to be the most versatile and easy-to-use design suite on the market, renowned for its productivity and allowing engineers to perform all of their tasks from one environment. Other usability improvements include support for multidimensional arrays in block diagrams; improved visualization of state machine transitions, simplified access to the most frequently used options, and easier and more flexible configuration of the whole environment.
Additional Improvements
Active-HDL 7.1 also includes new VHDL and Verilog lint tools, all new MATLAB and Simulink interfaces (exclusive to Aldec), and smart incremental compilation for Verilog.
"The increased simulation performance of Active-HDL 7.1 will provide an enormous gain to our already leading edge design entry, simulation and debugging solution," stated Laura Consoli Product Marketing Manager for Aldec. "Adding the debugging improvements for SystemVerilog will provide a completely new level of support from Aldec."
Pricing and Availability
Active-HDL conforms to IEEE standards for VHDL and Verilog and provides a complete FPGA vendor-independent solution. Active-HDL 7.1, which is available today, includes a multi-design workspace, HDL editor, state machine editor, block diagram & schematic editors, automatic testbench generation, simulation design profiler, signal agent, linting, waveform viewer, SystemC and a choice of VHDL, Verilog/SystemVerilog or mixed-VHDL/Verilog/SystemVerilog/EDIF simulation. Active-HDL 7.1 is sold directly from Aldec and all sales include one year of product maintenance. For a FREE evaluation copy of Active-HDL 7.1, please visit our company’s website at http://www.aldec.com/products/active-hdl.
About Active-HDL
Active-HDL is a Windows®-based, completely integrated, high performance HDL design and simulation environment. It supports VHDL, Verilog, SystemVerilog, SystemC and EDIF from design entry through implementation. Active-HDL provides the fastest simulation runs for all designs, regardless of source language or target silicon, including those with embedded devices.
About Aldec
Aldec, Inc., a 21-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. The company strongly believes that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
