OSVVM: Making VHDL transaction-based testbenches simple, readable and powerful - FirstEDA
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OSVVM: Making VHDL transaction-based testbenches simple, readable and powerful

Blog by Jim Lewis, VHDL Verification Specialist, OSVVM author, VHDL Trainer

Just because your design is complex does not mean your testbench needs to be. In OSVVM we have found that with proper abstractions we can create simple, readable, and powerful testbenches.

 

In OSVVM 2016.11 we released the transaction-based modeling approach we have been using for the past 20 years in our verification practice and classes. Looking at its block diagram, you will notice that its architecture looks similar to SystemVerilog + UVM.

 

Just like SystemVerilog, the OSVVM approach has a top-level sequencer, here named TestCtrl; it has verification models, CpuModel, UartTx, UartRx, and Memory; it has a top level testbench, sometimes called a test harness, named TbMemIO; and finally it has connections between the test sequencer and the models which we implement with OSVVM interfaces.