FirstEDA press releases
Please check back regularly for news of upcoming events.
| 2 November 2007 | Sequence Design |  |
| Press Release: Sequence Extends Low-Power Leadership: Two New Patents, CTO Frenkil Featured In New Design Tome |
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| 31 October 2007 | Aldec |  |
| Press Release: Zuken and Aldec Deliver New Design Solution: CADSTAR FPGA |
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| 12 March 2007 | Aldec | |
| Press Release: Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design |
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| 5 March 2007 | Aldec | |
| Press Release: Aldec releases 64-bit mixed HDL Simulator |
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| 5 March 2007 | Aldec | |
| Press Release: Aldec Signs Agreement with POSDATA |
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| Riviera-Pro™ HDL simulation environment to support POSDATA WiMAX product development | ||
| 8 January 2007 | Aldec | |
| Press Release: Lattice And Aldec Sign Mixed-Language Simulator Agreement |
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| Lattice Becomes the Only FPGA Company to Offer a Mixed Language Simulator Based on Aldec's Active-HDL Designer Edition Tools | ||
| 8 January 2007 | Synplicity |  |
| Press Release: Synplicity Revolutionizes ASIC Verification Methodology with new TotalRecall Technology |
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| Technology Provides High-Speed Verification and Complete Bug Visibility | ||
| 8 November 2006 | Aldec | |
| Press Release: Aldec Announces Support for Altera's Stratix III Devices |
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| 6 November 2006 | Aldec | |
| Press Release: Actel And Aldec Partner To Offer High-Reliability Design Solutions For Aerospace And Avionics Markets |
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| Companies Deliver Solutions for DO-254 Verification and Flash-Based RTAX-S Prototyping | ||
| 16 October 2006 | Aldec | |
| Press Release: Aldec Strengthens Verilog Simulator in Riviera-PRO™ |
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| 10 July 2006 | Aldec | |
| Press Release: New Release of Riviera 2006.06 Supports Open IP Encryption Initiative |
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| 23 May 2006 | Aldec | |
| Press Release: Aldec Granted New Patent On Automatic ASIC Prototyping |
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| 15 May 2006 | Synplicity | |
| Press Release: Synplicity Announces Full Support for New High-Performance Virtex-5 Devices from Xilinx |
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| Synplify Pro Software Delivers Best-in-Class Synthesis Support for Industry's First 65-nm FPGAs | ||
| 15 May 2006 | Synplicity | |
| Press Release: Synplicity and Xilinx Create Design Task Force to Tackle Timing Closure for Ultra High-Capacity FPGAs |
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| Engineering Teams Collaborate on Design Flow for Next-Generation 65-nm Devices | ||
| 15 May 2006 | Aldec | |
| Press Release: Lattice Semiconductor and Aldec deliver Quality Design Solution |
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| 9 May 2006 | Aldec | |
| Press Release: Altera's Quartus II 6.0 offers integrated HDL support for Aldec's Simulator |
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| 1 May 2006 | Synplicity | |
| Press Release: Synplicity and Actel Strengthen OEM Relationship for Best-in-Class EDA Solutions |
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| Companies Deliver Unparalleled Value to FPGA Designers | ||
| 17 April 2006 | Aldec | |
| Press Release: Aldec's Regression Automation enables Renesas to manage 10,000 HDL Simulators concurrently |
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| 17 April 2006 | Aldec | |
| Press Release: Server Farm Manager (SFMT) automates the process of HDL verification over the network |
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| 13 April 2006 | Aldec | |
| Press Release: Evatronix Verifies a Core with 50 Billion Legal Configurations Using Aldec Tools |
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| 11 April 2006 | Synplicity | |
| Press Release: Synplicity's Enhanced Synplify Pro Software Delivers Significantly Greater Quality of Results |
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| Altera's Stratix II and Stratix II GX Customers Can Achieve Up to a 20 Percent Performance Boost Over Earlier Versions | ||
| 30 March 2006 | Aldec | |
| Press Release: Aldec's Verilog Simulator with full support for Sun Microsystems Open-Source UltraSPARC T1 Processor Core is available at no cost for 90 days |
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| 20 February 2006 | Aldec | |
| Press Release: Aldec Active-HDL Student Edition distributed by Walmart and Barnes & Noble |
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| 10 February 2006 | Aldec | |
| Press Release: Aldec Appoints FirstEDA as new distributor in the United Kingdom and Ireland |
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| 29 December 2005 | Synplicity | |
| Press Release: Synplicity Extends Leadership Position in the FPGA Synthesis Market |
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| Latest Data Makes Synplicity the FPGA Synthesis Market Share Leader for the Fifth Consecutive Year | ||
| 31 October 2005 | Aldec | |
| Press Release: Aldec Releases Active-HDL 7.1 with New Simulation Technology and SystemVerilog Support |
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| 13 June 2005 | Concept Engineering |  |
| Press Release: Concept Engineering Releases GateVision® PRO - a Debugging Tool for the Verification of Complex Chips |
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| New GateVision PRO gives designers more control over gate-level debugging of ICs, SoCs, IP blocks, FPGAs | ||
| 8 June 2005 | Synplicity | |
| Press Release: Synplicity to Demonstrate Push-Button FPGA Physical Synthesis Technology at DAC 2005 |
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| Graph-Based Physical Synthesis Technology Can Deliver a 5 to 20 Percent Performance Boost for 90nm FPGAs | ||
| 14 April 2005 | Concept Engineering | |
| Press Release: Concept Engineering Improves Transistor-Level Debugging and Optimization for Chip Designers Using Cadence Virtuoso Schematic Editor Environment |
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| New SpiceVision PRO option automatically generates schematic fragments for export to Cadence's Virtuoso design technology | ||
| 13 December 2004 | Synplicity | |
| Press Release: Synplicity Increases Market Share in the FPGA Synthesis Market In 2003 |
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| Synplicity Share of the FPGA Synthesis Market Greater Than All Competitors Combined | ||
| 1 June 2004 | Concept Engineering | |
| Press Release: Concept Engineering Adds 64-bit Support to SpiceVision®PRO to Accelerate Debug and Analysis of Complex Digital, Mixed-Signal, and Analog ICs |
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| SpiceVision PRO allows transistor-level analysis and navigation of largest, most complex designs | ||
| 13 May 2003 | FirstEDA |  |
| Press Release: Industry News - EDA Forum 2003 |
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| FirstEDA announces a dedicated UK-based EDA Forum to be held on 11 June at Heathrow, London | ||
