Active-HDL - FirstEDA
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Active-HDL

FPGA Design & Simulation / FPGA / FV

Active-HDL is a Windows-based, integrated design creation and simulation solution for engineers working on projects ranging from simple PLD ‘glue logic’ all the way up to several-million-gate system-on-chip FPGAs.

Active-HDL features an Integrated Design Environment (IDE) that includes a full HDL and graphical design tool suite and an RTL/gate-level mixed-language simulator, ideal for the rapid development and verification of designs. It also features a design flow manager that invokes more than 120 EDA, PLD and FPGA tools during design entry, simulation, synthesis and implementation. Active-HDL supports industry leading FPGA devices from leading vendors including Altera, Atmel, Lattice, Microsemi (Actel), Quicklogic and Xilinx.

FIRST AND FOREMOST

Active is the key word. Active-HDL is an extremely powerful yet easy-to-use EDA tool for designers working in isolation (on one or more projects) or within a team-based environment. As an IDE, Active-HDL has all the functionality needed to support you – and automate key tasks – throughout every stage of the design flow.

DISPLAY FEATURES AND BENEFITS

Project Management

  • The configurable flow manager allows users to remain in a single easy-to-use integrated design environment throughout the entire design flow
  • Unified Team-based Design Management maintains uniformity across local or remote teams

 

Graphical/Text Design Entry

  • Quickly deploy designs by using Text, Schematic and State Machine
  • Distribute or deliver IPs using a more secure and reliable Interoperable Encryption standard

 

Simulation and Debugging

  • Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog (Design) and SystemC
  • Ensure code quality and reliability using graphically interactive debugging and code quality tools
  • Perform metrics driven verification to identify unexercised parts of your design using Code Coverage analysis tools
  • Improve verification quality and find more bugs using ABV – Assertion-Based Verification (SVA, PSL, OVA)
  • Connect the gap between HDL simulation and high level mathematical modelling environment for DSP blocks using MATLAB/Simulink interface

 

Documentation HTML/PDF

  • Abstract design intelligence and represent them in easy to understand graphical form using HDL to schematic converter
  • Share designs quickly with auto-generate Design Documentation in HTML and PDF.
FirstEDA has represented and supported Aldec Active-HDL since 2006, our support team includes engineers who have worked with Aldec and Active-HDL since 1999 and as a result we are able to offer unparalleled local support. No matter what your level of experience, Active-HDL’s ease-of-use and intuitive functions allow you to design quickly and efficiently whilst providing class-leading simulation performance and features.