Product Datasheet - Aldec - Active-HDL
Active-HDL
Complete HDL Design & Verification
Active-HDL Overview
The Active-HDL suite is a comprehensive and totally integrated environment for digital IC design and verification that employs hardware description languages and C/C++ solutions. It provides engineers and design teams with tools for efficient and vendor independent design implementation and testing. The Active-HDL suite has been designed based on customer suggestions and feedbacks to ensure highest design productivity and remarkable ease-of-use.
Active-HDL supports even the most complex FPGA and ASIC designs by providing the following key features:
- Design Entry
- High Performance Simulator
- Debugging
- Co-simulation
- Automated Testbench Generation
- Design Data Management
- FPGA Vendor Support
- Coverage and Profiler Metrics
- Documentation
- Legacy Design Support
Designers can choose between intuitive graphical editors and efficient text-based design entry tools. The diagram editors speed the description of the hardware structure as well as the behaviour of control units in a way familiar to most engineers. Numerous wizards help jump start with ready-to-use document templates with block diagrams, state diagrams, or source code. Additionally Active-HDL includes a utility for converting a textual description into a graphical document that can be viewed and edited in a graphical design entry tool.
Unique single-kernel simulation technology allows simulation of a mixture of Verilog, VHDL and SystemC language constructs. Optimised HDL compilers generate highly efficient processor-native code that ensures both outstanding performance and good signal visibility for detailed debugging. Aldec's industry-proven solution is the only simulator that is capable of handling EDIF netlists, enabling verification of legacy schematic designs together with newer HDL-based design sections. Flexible architecture and standard programming interfaces enable instant integration with other EDA tools and in-house solutions.
Active-HDL's has a rich set of debugging and simulation results visualisation tools. Exploration of the project structure is simplified with a rich set of utilities that display the relationships between various design elements. Along with the interconnections, the signal and variable values can be observed in a variety of tools like Waveform Editor, Watch Window, Memory View window and Call Stack. Fine control over the execution process is provided by code tracing capability and advanced, selective breakpoint management.
To meet the ever-growing complexity of electronic systems, Active-HDL offers co-simulation interfaces such as MathWorks' MATLAB® and Simulink®, enabling system designers to trace mathematical modeling to HDL code implementation. Engineers that implement Celoxica's Handel-C in their flow can employ Active-HDL's co-simulation interface to combine their Handel-C models with HDL and SystemCT design blocks.
Automated Testbench Generation
To speed functional verification, some powerful testbench generation automation features have been provided. A testbench for any design unit can be generated from waveforms created in waveform editor or generated during a simulation run. For control units, a set of comprehensive testbenches can be produced automatically to cover all states and transitions defined on a state diagram created with Active-HDL.
Active-HDL manages all information related to a design or multiple designs contained within a workspace. It facilitates configuration of compilation and simulation processes, while handling and organising source and log files that are created throughout consecutive design phases. To enable efficient teamwork and ensure proper control of changes introduced by the design group members, archiving utilities and an interface to source revision control systems have been incorporated into the Active-HDL suite.
Active-HDL is tailored to support designers working with FPGA families from different vendors. The Active-HDL environment has interfaces to third party synthesis and place-and-route tools. Users can select files for synthesis and implementation, set options within the selected tools and invoke process either in batch mode or launch an application GUI directly from Active-HDL's Design Flow Manager. As a part of the suite, pre-compiled Verilog and VDHL libraries of all FPGA silicon vendors are delivered in a ready-to-use form. In addition, libraries that support schematic entry from Block Diagram Editor are provided for Xilinx® device families.
The coverage of verification analysis is crucial in minimising the risk of design re-spin due to undetected flaws. The Active-HDL suite comes with various utilities that allow measurement of the HDL code coverage quality and signal activity. Code Coverage and Toggle Coverage identify the lines of code that have not been executed, branches of conditional statements that have not been entered and find signals that have not changed their values as expected. The Profiler feature helps to optimise the simulation performance by measuring the time spent on the execution of the HDL statements and pointing out the parts of code that can be either modified to reduce simulation time or accelerated in hardware.
Active-HDL allows exporting all files related to a design into HTML documents, PDF and graphic files. Individual documents, entire designs or workspaces that contain multiple projects can be printed with convenience. Conversion from text based HDL description into graphical documents can significantly improve legibility of electronic or printed documentation.
Migration and maintenance of schematic design in Active-HDL is enabled by support of the EDIF netlist format and legacy design import features. Projects made with use of the Viewlogic and the Active-CAD/Xilinx Foundation Series software can be read and converted into graphical design entry documents.
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