FirstEDA presents Aldec
Our role is as a provider of Electronic Design Automation solutions to design engineers.
 AldecHDL Design Entry & Simulation |
Superior solutions for HDL design entry and simulation; Active-HDL has been used by over 10,000 engineers worldwide whilst Riviera provides class-leading verification performance and capacity. |
Aldec Solutions
Active-HDL Complete FPGA Design and Verification Suite
Active-HDL has been used by over 10,000 electronic design engineers worldwide since it's introduction in 1997. The growing popularity of Active-HDL is attributed to its ease-of-use and high performance. Since most design engineers use this tool throughout their entire day, it has been designed for productivity and reliability. When it comes to verification, Active-HDL offers top performance of VHDL and Verilog simulation in both functional and timing modes and the capacity to simulate multi-million gate designs. Aldec recommends Active-HDL for all HDL designers who like to lead in design productivity and perform all design tasks within the same desktop environment.
Riviera-PRO HDL Verification Suite
Riviera-PRO has been designed for verification of the largest designs. Designed from scratch to handle very large designs, Riviera is free from typical bottlenecks found in tools designed for smaller projects. With Riviera PRO you can work in a 64-bit environment with tens of gigabytes of memory and millions of signals. With the focus on performance of VHDL and Verilog and emerging HDL standards like Assertions, SystemVerilog and SystemC - Riviera is the top choice for companies demanding the best tools for large designs. Riviera works on Windows, Linux and Sun Solaris operating systems and supports server farm configurations.
HES Hardware Embedded Simulation
When software simulation takes too long, consider hardware-based verification. HES is the high-performance verification environment which allows the designer to download all or portions of the design into prototyping boards for high speed verification, which is up to 100 times faster than software simulation. The unique patented solution in HES allows automatic detection and conversion into hardware those design sections that consume most of simulation time.
