HES-DVM - FirstEDA
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HES-DVM

Hardware Assisted Verification / HW–V / PROTO / ASIC

HES-DVM is a fully automated verification and validation system for SoC ASIC designs of 200M+ ASIC gates. Aldec’s FPGA Hardware Emulation Solution is based on the latest Xilinx Virtex-7 devices and is capable of simulation acceleration, and SCE-MI transaction co-emulation.

RTL Debug

HES-DVM provides full control of the system in both acceleration and co-emulation with SCE-MI. As well as control, HES-DVM provides 100% design visibility and with Aldec’s HVD technology the impact on system performance can be minimised.

Debug Capabilities
  • High performance debug infrastructure (HMDB bus)
  • Flexible static probes, advanced embedded logic analyser for at-speed RTL debug
  • Dynamic debugging with HVD technology
  • Emulation triggering and control capabilities
  • Memory viewer and write access tools including API
Hybrid Virtual Prototyping

Utilising virtual platforms with HES-DVM’s co-emulation interface, developers are able to connect SystemC TLM modules to their hardware DUT via high speed transactors. HES-DVM memory management API enables developers to load applications to program memory, decreasing overall system boot-time.

HES a Scalable System

The use of Xilinx devices is a cost-effective solution for hardware emulation and enables replication of the system for software development and verification regression systems. Aldec supports customer FPGA systems as part of its custom board support.

Time to Emulation / TTE

The use of Xilinx devices is a cost-effective solution for hardware emulation and enables replication of the system for software development and verification regression systems. Aldec supports customer FPGA systems as part of its custom board support.

FIRST AND FOREMOST

The Design Verification Manager (DVM) environment enables system ‘bring-up’ times of weeks, as opposed to months. This allows earlier hardware and software integration in the project schedule, resulting in reduced development time and a shorter time to market.

DISPLAY FEATURES AND BENEFITS
  • Automated system build, setup, run and debug
  • SCE-MI 2 compiler
  • ASIC to FPGA conversion
  • RTL debug with 100% visibility
  • Hybrid Virtual Prototyping
  • Custom board support
  • Scalable system for software development and verification regression
HES-DVM is used by semiconductor companies developing complex SoC ASICs as well as IP providers. Typically used in combination with simulation and traditional hardware accelerators, FPGA base systems provide unmatched scalability and performance.