Product Datasheet - Aldec - HES Acceleration
HES Acceleration
Hardware Embedded Simulation
HES Overview
HES is a unified hardware acceleration solution that maximises simulation performance and accelerates ASIC and FPGA design verification by 10x-50x over traditional methods. The unified solution provides greater speed and efficiency by bringing together many different design and verification elements in one seamless system.
HES's concept of the acceleration lies in the design partitioning between the software simulator and the PCI acceleration board. This enables the designer to offload portions of the design from the software simulator providing a significant performance increase throughout the verification cycle.
HES's acceleration solution consists of three main components. Any industry-standard HDL simulator, an acceleration board(s) with single board capacity of up to 12 million gates and the Design Verification Manager for set-up and project management.
- HES components:
- Verification modes
- Co-verification of ARM Systems
- SystemC/Acceleration board co-simulation
- Embedded Memories
- Debugging
- Assertions
- ASIC to FPGA Clock Conversion
- Incremental Synthesis
- C-Models Overview
- Automatic Design Partitioning in the Simulation Mode
- VHDL Testbench Conversion to C++
HES includes a Design Verification Manager (DVM) to easily setup designs for accelerated verification. Since only synthesizable parts of the design can be placed in the acceleration board, the DVM enables effective partitioning of the design, leaving all non-synthesizable logic in the simulator and implementing on-demand all synthesizable logic to the acceleration board. The DVM automatically generates all files needed to run the accelerated verification process.
High Performance HDL Simulator
HES interfaces to all industry-standard HDL simulators. Every simulator interface provides full HES system functionality. Aldec's Riviera HDL Simulator untilises common kernal simulation technology that allows simulation of a mixture of Verilog®, SystemVerilog®, VHDL, and SystemCT. Optimised HDL compilers generate highly efficient native compiled code that ensures both outstanding performance and visibility for debugging. Aldec's industry-proven solution is the only simulator that is capable of simulating EDIF netlists enabling legacy schematic design verification. Flexible architecture and standard programming interfaces enable integration with other EDA tools or in-house solutions. Optimised direct kernel support for Aldec simulation including external interface to third party simulation tools.
The HES acceleration board is an FPGA based board with standard PCI interface. During verification the acceleration board is completely synchronised with the software simulator and runs on the simulator clock frequency (10-100 of KHz). This enables the designer to have visibility of the accelerated design in the simulator. The capacity of a single acceleration board varies from 1 to 12 million FPGA gates. The number of boards in one system is limited only by the number of available PCI slots on a workstation.
HES provides several different verification modes depending on the design development stage, components, testbench, etc. Based on the designers verification needs the simulation can run at different speeds providing variable debug visibility.
Co-verification of ARM Systems
HES with ARM provides a complete high-speed co-verification and debug environment for complex embedded software/hardware co-development. Utilising hardware processors and memory from ARM the entire environment is connected through a daughterboard to HES's hardware accelerator and industry-proven common kernel simulator. The co-verification of the following ARM systems is supported:
- ARM 946 with AHB
- ARM 926 with AHB
- ARM 920T with AHB (AHB wrapper is used)
- ARM 720T with ASB
ARM development kit and devices are sold separately.
SystemC/Acceleration board co-simulation
HES provides interface allowing direct communication of SystemC testbench and the design implemented to the board at the cycle level. DVM automatically generates SystemC wrapper that is used for the connection of the UUT module in the board with SystemC testbench.
The ability to map different memory modules of the design to the on-board memory (up to 6GB) allows HES to offload the usage of PC's system memory and accelerate the simulation speed dramatically.
HES provides the ability to view signals from the modules in the acceleration board directly in the Riviera Waveform. User can specify internal signals or module in hardware that will be monitored and observed in the simulator.
HES supports OpenVera Assertions (OVA), PSL/Sugar, Open Verification Libraries (OVL) and C/C++/SystemCT constructs both in the software simulator and synthesizable constructs in hardware.
Note: Hardware is limited to OpenVera Assertions only.
Automatic clock conversion allows designers to implementation ASIC type designs into the FPGA architecture of HES. Automatic detection of both internal and external clocks is supported including delays for input/output clock signals and fixes race conditions between hardware and software. If the design contains several sophisticated internal clock domains the clock analysis feature can automatically correct timing consistencies of the design (particular important for ASIC devices). This simplifies hardware acceleration while saving the designer time and providing higher design quality.
HES provides automatic incremental synthesis of all sub-modules eliminates the need to continue synthesizing the entire design after every iteration. Incremental synthesis also aids in the partitioning process between software and hardware when using multiple acceleration boards.
HES provides an easy to use "plug-in-like" API for C/C++ based simulation models of hardware (C-Models). Simulation models in C/C++/SystemC can communicate with accelerator boards directly without the HDL Simulator in between to transfer data. C-Models can selectively replace any HDL design block. This reduces the load on the software simulator. Note that the top-level testbench can also be written in C, C++, or SystemC.
Automatic Design Partitioning in the Simulation Mode
HES divides the module between hardware resources automatically that allows adding to the acceleration hardware an entire design top-level without the concern on how to split the design modules between available acceleration boards.
VHDL Testbench Conversion to C++
The VHDL2CPP converter transforms the VHDL testbench to C++ source ready for compilation to an executable file (a simplified simulation kernel) that runs the whole simulation with the interconnected acceleration boards. It speeds hardware acceleration process by applying C++ executable files in place of VHDL or Verilog testbenches. This design simulation process is substantially faster than using simulators driven by VHDL or Verilog testbenches.
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