FirstEDA presents Aldec
Our role is as a provider of Electronic Design Automation solutions to design engineers.
 AldecHDL Design Entry & Simulation |
Superior solutions for HDL design entry and simulation; Active-HDL has been used by over 10,000 engineers worldwide whilst Riviera provides class-leading verification performance and capacity. |
About Aldec
Established in 1984 by founder and CEO Dr. Stanley M. Hyduke, Aldec, Inc. is a self-funded, privately held organisation that continues to deliver high quality, performance-driven EDA products. Dr. Hyduke's 42 years in the industry provide him with a unique knowledge and understanding of the trends and technologies that will most benefit hardware engineers. Because of this clear focus, Aldec has evolved into one of the best-known names in design verification.
Since 1997, Aldec has been focused on providing easy-to-use VHDL and Verilog design entry and simulation products to support programmable logic designers; its products were well accepted by customers who were transitioning from schematic-based design to a mixed schematic/HDL environment and pure HDL code.
With the density of FPGA/CPLD devices continuously growing, ASIC designers are beginning to utilise FPGA/CPLDs for prototyping and finished products. Responding to this need, Aldec has added a new line of hardware/software co-verification products utilising hard and softcore processors to address the market requirements for new verification methodologies.
Aldec's industry-proven, common kernel HDL simulation technology supports all operating systems (Window, Linux and UNIX) for both 32 and 64-bit configurations. In addition to traditional, high-performance HDL support, Aldec also supports SystemCT, SystemVerilogT, Assertions (OVA, SVA and PSL), hardware acceleration and co-verification from a single design platform.
Aldec provides a broad spectrum of HDL verification tools to support every market segment, ranging from entry-level HDL users who target low density FPGAs to users requiring high performance tools for Assertion-based verification designs, as well as hardware-based acceleration and co-verification methodologies to best meet their time to market requirements.
Aldec continues to deliver the highest mixed simulation performance for all market segments.
Focus
Aldec provides highly-integrated solutions for the design engineering community by supporting new methodologies that speed the overall design verification process. The company has developed a world-class simulator that addresses users' requirements for common kernel simulation, in addition to supporting new design verification methodologies that include SystemCT, SystemVerilog, Assertions-based Verification (ABV), hardware acceleration and co-verification from a single platform.
Customer Profile
Over 3,000 commercial companies, as well as 1,500 accredited academic facilities, utilise Aldec's design entry and mixed language simulation tools to expedite their design and verification cycles. Aldec's customers vary in industry from Telecom, Industrial, Military and Space Agency, Consumer Electronics and IP development companies. Aldec's products provide innovation and functionality to every market segment, and as customers' requirements for high level verification tools grow, so does Aldec's breadth of product offerings and technology.
