Product Datasheet - Aldec - Riviera-PRO
Riviera-PRO
High-performance ASIC and Large FPGA Verification Solution
Riviera-PRO Overview
Riviera-PRO is a high-performance ASIC and large FPGA verification solution. A common kernel simulator supports VHDL, Verilog, EDIF, SystemC, SystemVerilog, SVA, OVA and PSL in a unified, advanced debugging environment.
- Extensive Language Support
- Compilation
- Simulation
- Simulation Databases
- Debugging
- Scripting and Batch Processing
- Support for C/C++/SystemC
- Assertion Based Verification
- Coverage
- Profiler
- Partner Interfaces
- 64-bit Computing
- Linting
Riviera offers the most extensive language support available on the market. VHDL, Verilog, EDIF, SystemC, SystemVerilog, SVA, OVA and PSL are all supported from a common kernel simulator eliminating the overhead associated with interfaces and providing high performance and ease of use.
Riviera uses its own compilers to compile VHDL, Verilog, EDIF and assertions. Popular, GPL-licensed gcc compilers are used for C/C++/SystemC compilation.
Riviera is the simulator of choice throughout all design stages, from system-level and behavioural simulations through gate-level and SDF-annotated netlists.
The simulator can save signal history to a simulation database. Signal waveforms can be displayed either interactively, during simulation or loaded from a database created in a previous simulation run.
Advanced debugging tools are provided, including a Waveform Viewer, an Advanced Dataflow window and a source code debugger. Simulations can be stopped on a code, signal or condition breakpoint.
Scripting and Batch Processing
The environment is easy to script. Multiple simulations can be run in the batch mode. The script interpreter supports TCL scripts.
C/C++ code can be easily hooked to the simulator with generic, IEEE-standardised VHPI and PLI interfaces. With the help of VHPI and PLI interfaces, designers can register callbacks on signals, force values in the simulated model or scan design hierarchy. SystemC is supported natively. SystemC modules are compiled to regular design libraries and integrate seamlessly with HDL models during simulation.
Assertions can be defined in PSL, OVA or the assertion subset of SystemVerilog. Assertions are simulated alongside regular HDL code. An Assertion Viewer and a Functional Coverage viewer (embedded in the Code Coverage Viewer) are available.
Statement Coverage and Branch Coverage collect execution counts for individual HDL statements and conditional execution paths. Coverage statistics can be viewed in a stand-alone Coverage Viewer. Coverage data can be further augmented with Toggle Coverage. Toggle Coverage measures design activity in terms of changes in signal logic values.
A tick-based profiler counts the number of CPU-ticks and the number of milliseconds required to execute each HDL statement. The profiling data is very accurate. It can indicate how to change your models so that they will simulate faster (through more efficient coding or hardware acceleration).
Riviera is an open solution. You can hook up your own applications to the simulation kernel using generic PLI and VHPI interfaces. Ready-to-use interfaces to third party tools are also available.
Riviera now includes 64-bit support. The 64-bit version is a batch mode, common kernel, multi-language simulator aimed at supporting large verification teams.
VHDL and Verilog linting are integrated with their respective compilers and perform additional checks during compilation to ensure code correctness. Linting is a standard debugging feature in Riviera PRO.
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