Superior solutions for HDL design entry and simulation; Active-HDL has been used by over 10,000 engineers worldwide whilst Riviera-PRO provides class-leading verification performance & capacity. ALINT is a cost-effective flexible design rule-checker for validating VHDL and Verilog code. Aldec's range of speciality solutions also covers DO-254 Compliance and Actel RTAX Prototyping.

Concept Engineering is the leading provider of standalone debugging solutions for RTL-level (RTLvision), gate-level (GateVision), transistor-level (SpiceVision) and mixed-level (SGvision).

HyperPlot is the undisputed standard for plotting in the semiconductor and EDA industries with over 35,000 engineers worldwide relying on its optimised print engine.