Product Datasheet - Sequence Design - Columbus
Columbus - Powerful Interconnect Modelling
RLC Extraction for Nanometer SoC Design
The Columbus product suite provides unparalleled RLC parasitic extraction accuracy and versatility to meet the design challenges at 90nm and beyond. Eliminate costly re-spins and tape out your designs with confidence knowing that interconnect parasitics won't compromise performance. Only Columbus's patented extraction engine delivers the precision needed to model on-chip variations in today's advanced process technologies, allowing you to reduce guardbands and achieve silicon success. Columbus offers both gate-level and device-level extraction capabilities, ensuring integration into your power, reliability and signal integrity flows for standard cell, custom digital, mixed signal and analogue designs.
Columbus-TURBO - High-Capacity Extraction for Nanometer Standard-Cell Design
Columbus-TURBO Highlights
- High capacity architecture extracts RC for both power rails and signal nets in 10M instance designs
- 3M+ net per hour speed using LSF compatible multiprocessing
- Extracts multi-level hierarchical designs comprising of nested standard cell and full custom blocks
- Models process variations and density-related effects including fill and metal slotting
- Supports Cadence, Magma and Synopsys place and route flows
Columbus-AMS - Accurate RLC Extraction For High-Performance Analogue
Columbus-AMS Highlights
- Graphical interface to Cadence Analogue Design Environment controls extraction without leaving Virtuoso
- Smart Probing lets you analyse R, L and C interactively
- Proven inductance extraction lets you model clocks, buses and other critical high speed signals
- Selective parasitic modeling around devices eliminates double counting
- Compact parasitic netlists give efficient circuit simulation
- Consistent accuracy, particularly around contacted FET's, reduces guardbands and increases confidence in tapeouts
- LSF-compatible multiprocessing accelerates large extraction jobs
- Supports Calibre, Diva, Assura LVS tools, GDS and LEF/DEF data Supports a wide variety of analog processes including IBM 5- through 8- series SiGe and CMOS-RF
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