FirstEDA presents Sequence Design
Our role is as a provider of Electronic Design Automation solutions to design engineers.
 Sequence DesignEnabling Power-Aware SoC Design™ |
Sequence Design-for-Power (DFP) solutions accelerate the development of high-performance, power-aware ICs by addressing the entire flow; micro-architecture and RTL through to gate-level. |
About Sequence Design
Sequence is in the Top 10 private EDA companies according to industry sources, of about 280 private companies addressing the complex system-on-a-chip (SoC) design flow today.
Sequence low power design tools are used by designers in wireless, graphics, mobile-computing, networking and ASIC markets.
Mission
Sequence's mission is to deliver a unique competitive advantage to sub-90 nm System-on-a-Chip (SoC) designers: a design-for -power (DFP) flow from RTL to sign-off.
Customers
Sequence has over 150 customers worldwide including top semiconductor companies such as NEC, Renesas, NVIDIA, Qualcomm, Texas Instruments, Samsung, Toshiba, FreeScale, Matsushita, LG Electronics, AMD and many others. Sequence's low-power flow has been adopted and certified by Dongbu HiTek (Korea) and STARC (Japan).
There are over 240 licenses of the front-end product, PowerTheater, and over 200 licenses of CoolProducts and Columbus installed on the physical implementation side. Sequence estimates over 900 tape-outs by designers and over 200 implementation tape-outs.
The Solution
Sequence Design-for-Power (DFP)™ flow encompasses a complete solution from micro-architecture and RTL through gate-level implementation.
During design, Sequence DFP flow offers 3 advantages:
- Early power analysis, at RTL, before it is too late to design proactively for power.
- A portfolio of power reduction and power debug solutions available at RTL, that have been shown to reduce power from 25% to 50%.
- Qualification of vectors for package selection and power grid design.
- Products:
- PowerTheater-65: RTL analysis and reduction.
- PowerTheater-Explorer: Cockpit and visualisation environment for power reduction.
During physical implementation, Sequence solves 3 main issues in power-aware SoC designs:
- Accelerated predictable power closure of large, (~900M transistors including memories and IP) high-performance designs with over 33% advantage in time to market.
- Ensuring power grid integrity with a comprehensive set of technologies.
- 20 - 40% power reduction capability which preserves timing and signal integrity (SI) with time-to-market savings of 7-10 days per SoC block.
- Products:
- CoolTime: Dynamic and static voltage-drop and electro-migration (EM) analysis for power grid design.
- CoolCheck: Vectorless, formal power-grid verification.
- CoolPower: Power reduction and optimisation concurrent with timing and signal integrity optimisation.
- Columbus-AMS: Foundation extraction technology which provides highly accurate 3-D, RLC-interconnect modeling for both full custom and SoC designs.
Sequence tools fit seamlessly with all major vendor flows, including Cadence, Synopsys and Magma.
