FirstEDA presents Sequence Design
Our role is as a provider of Electronic Design Automation solutions to design engineers.
 Sequence DesignEnabling Power-Aware SoC Design™ |
Sequence Design-for-Power (DFP) solutions accelerate the development of high-performance, power-aware ICs by addressing the entire flow; micro-architecture and RTL through to gate-level. |
Sequence Power-Aware SoC Design Flow
Sequence enables power-aware SoC design from system level to signoff. Sequence has fortified its leadership in RTL power, dynamic voltage drop and signal integrity closure with the unveiling of exciting new solutions for power at Electronic System Level (ESL) and concurrent physical optimisation of leakage power (MTCMOS power gating and multi- Vth), active power and dynamic voltage drop. Sequence offers products for a system level to signoff flow wherein power analysis and optimisation are seamlessly integrated at each stage in the user's existing design and implementation flow. Sequence's unique solution enables SoC designers to reduce time-to-market and chip costs for power-aware applications.
;) |
Select graphic for a larger picture |
PowerTheater - Early Power Management For Nanometer SoC Design
Power Theater™ is a comprehensive set of power tools that help you create maximum power efficiency for your SoC designs. Sequence is the only company delivering power software focused at the architectural, RT and gate levels of abstraction. Integration of PowerTheater with the leading ESL design tools allows designers to explore alternate architectures and optimise for performance, area and power requirements at levels of abstraction higher than the RT level. In partnership with ESL vendors enabling performance and area exploration, Sequence takes the lead in tackling the power exploration problem.
Electrical Integrity Analysis for Nanometer SoC Design
CoolTime™ is the industry's leading cell-based electrical integrity solution for concurrent analysis of voltage drop, power, electromigration (EM), timing and signal integrity (SI) for nanometer SoC designs. Eliminating the need for multiple point tools and iterations, CoolTime renders accurate and convergent analysis of interdependent electrical effects. CoolTime shares a common platform with CoolPower™ optimisation to ensure rapid design closure for dynamic voltage drop, leakage power, EM, timing and SI effects.
Power Integrity Closure for Nanometer SoC Designs
CoolPower™ is the industry's leading cell-based Power Integrity solution for concurrent optimisation of power, dynamic voltage drop, timing and signal integrity (SI) for nanometer SoC designs. CoolPower predicts and corrects design closure issues both before and after routing. It gives users the ability to interactively optimise hierarchical, multi-million gate SoC designs at the block-level as well as full-chip level. CoolPower integrates into popular third-party place and route tools to enable existing physical flows to reach fast, predictable design closure in silicon geometries below 130 nanometers (nm).
Columbus - RLC Extraction for Nanometer SoC Design
The Columbus™ product suite provides unparalleled RLC parasitic extraction accuracy and versatility to meet the design challenges at 90nm and beyond. Eliminate costly re-spins and tape out your designs with confidence knowing that interconnect parasitics won't compromise performance. Only Columbus's patented extraction engine delivers the precision needed to model on-chip variations in today's advanced process technologies, allowing you to reduce guardbands and achieve silicon success. Columbus offers both gate-level and device-level extraction capabilities, ensuring integration into your power, reliability and signal integrity flows for standard cell, custom digital, mixed signal and analogue designs.
Design For Power: Sequence Power-aware SoC Design Flow 
(1,393Kb)
