Hardware Assisted Verification - FirstEDA
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Hardware Assisted Verification


We promote the use of FPGAs for hardware assisted verification. The use of standard parts from FPGA vendors enables a scalable system that is cost effective for use in FPGA verification, software development platforms (such as hybrid virtual prototypes) and system-level pre-silicon regression testing. As well as providing off-the-shelf systems we support in-house developed FPGA boards through Aldec consulting.

The complexity and size of modern ASICs has surpassed what can be simulated with conventional RTL simulators. This has resulted in a renaissance for hardware assisted verification, also referred to as emulation. As well as significant hardware verification problems, the amount of software, specifically hardware dependent software, has also increased in today’s SoC. For some time now FPGA prototypes have been used as the pre-silicon software development platform. Such systems are now being used earlier in the design process, resulting in greater use of FPGA based systems for hardware verification.

Hardware Assisted Verification / HW-V / PROTO / ASIC

HES-DVM is a fully automated verification and validation system for SoC ASIC designs of 200M+ ASIC gates. Aldec’s FPGA Hardware Emulation Solution is based on the latest Xilinx Virtex-7 devices and is capable of simulation acceleration, and SCE-MI transaction co-emulation.

Aldec HES-7
ASIC Prototyping / HW-V / PROTO / ASIC

HES-7 provides SoC and ASIC verification and validation teams with a scalable and high-quality FPGA-based ASIC prototyping solution. Each HES-7 board with dual Xilinx Virtex-7 2000T has 4million FPGA logic cells (or up to 24million ASIC gates of capacity) not including the DSP and memory resources.