DO-254 / Safety Critical - FirstEDA
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DO-254 / Safety Critical


From DO-254 and EN-80 for the aerospace industry, to ISO-26262 in the automotive; requirements driven design and traceability are key when it comes to safety critical design. Defined methodologies and tools are essential in managing such designs successfully; Because of this we offer a number of tools and solutions that are specifically intended to aid in design and verification for safety critical and mission critical applications.

When the successful implementation of your design can make the difference between life and death, you need to be absolutely confident that your design is fit for purpose, and that you have taken all possible steps to assure that it won’t fail. Design assurance guidance, in the form of standards such as DO-254, are a means of compliance in the design of complex electronic hardware devices.

Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.

Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO-CDC is a design verification solution focused on asynchronous clock domain crossing analysis and used to manage metastability in designs with multiple clock domains.

Aldec Spec-TRACER
Requirements Lifecycle Management / REQ-M / SAFETY

Spec-TRACER is a unified requirements lifecycle management solution designed specifically for FPGA and ASIC designs. It facilitates requirements capture, management, impact analysis, traceability and reporting. Spec-TRACER seamlessly integrates with your Windows-based HDL design and simulation tools and also integrates directly with IBM Rational DOORS.

Aldec DO-254 CTS
FPGA Level In-target Testing / SAFETY

DO-254/CTS is a fully customised hardware and software platform that augments target board testing to increase verification coverage by test and to satisfy the verification objectives of DO-254/ED-80.

OneSpin Solutions 360 DV-Inspect
Automated Static Analysis / FPGA / FV / SAFETY / ASIC

360 DV-INSPECT increases the productivity of existing design and verification flows by adding push-button formal analysis; which can start as soon as the design under test (DUT) has been compiled, and independently of testbenches. In this way, critical bugs can be found much earlier than with a purely simulation-based flow.

OneSpin Solutions 360 DV-Verify
Assertion-based Verification / FPGA / FV / SAFETY / ASIC

360 DV-Verify is a unified coverage-driven assertion-based verification solution. The combination of a fully functional, high-performance formal property analyser with a unique assertion coverage evaluator eliminates the guesswork from quality assertion generation.

OneSpin Solutions 360 EC-FPGA
Functional equivalence checking / FPGA / FV / SAFETY

360 EC-FPGA ensures systematic errors are not introduced in the RTL implementation process of programmable devices.

Sigasi Studio
VHDL code editing, browsing & checking / FPGA / SAFETY / ASIC

The Sigasi Studio platform was developed specifically to make HDL design easier and more efficient. It is based on the Eclipse platform and brings the same kind of real-time code checking assistance that software engineers have enjoyed for years firmly into the hardware arena.