Online VHDL Training

Our engineering experiences, past and present, add immense value to all of our courses and ensure both the in-person and online live VHDL training you receive are fit-for-purpose. For instance, we can teach you best-practice coding techniques and guide you on how to formalise your verification processes; all of which helps reduce project timeframes.

Our VHDL training courses are engaging, practical and sociable, and we certainly haven’t lost sight of the fact that engineering is both interesting and rewarding. Whether attending to learn new skills or to enhance your current ones, you will be mixing with like-minded individuals, all of whom are keen to learn new techniques and methodologies that will further their careers.

All of our in-person and interactive online courses include 50/50 lecture and lab time. See the details and online and in-person VHDL training schedule below.

Why choose FirstEDA?

• Our in-person and live online VHDL courses are taught by time-served engineers with over 60 years combined experience in the industry
• We can bring the in-person or online live training to you, and tweak course content to meet any specific requirements you may have
• Our live online courses are cost effective and are highly reviewed

“The importance of keeping your engineering skills current and learning appropriate methodologies cannot be over-emphasised. Having worked with FirstEDA for a number of years now I have seen hundreds of engineers complete our courses and return to their organisations enlightened and enthused.” – Jim Lewis, SynthWorks.

VHDL is a hardware description language (HDL) used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays (FPGA) and integrated circuits (IC). VHDL is an abbreviation of VHSIC (very high speed integrated circuit) Hardware Description Language.

The most recent Wilson Research Group ASIC and FPGA Functional Verification Study shows that over 60% of worldwide FPGA design is in VHDL. In Europe this figure is higher still. VHDL is a deterministic, highly self checking language and is therefore the preferred HDL for Avionics and Milaero, and for anyone designing safety critical and high reliability systems. VHDL is also the most up to date HDL available, and can be used for both design and verification, without the need to switch to confusing object oriented techniques for verification.

As a European company supporting European customers, we are committed to VHDL. We offer three Language & Methodology courses: VHDL for FPGA designers (which provides a thorough background in the writing, use and application of synthesisable VHDL); Intermediate VHDL (which pushes further into applications) and Advanced VHDL Testbenches & Verification (a.k.a. ‘OSVVM Boot Camp’ and the content of which includes transaction-level modelling, self-checking, functional coverage and constrained random test benches).

Our In-Person & Online Live Training Courses

VHDL for FPGA Designers (3-days online)

Our introductory VHDL training course provides a thorough background in the use and application of synthesisable VHDL in digital hardware design.

The training is structured around a set of basic component building blocks to demonstrate the application of VHDL.

This is the first part of our online VHDL training series, covering basic concepts and syntax relating to the circuit structures covered, and gives the FPGA designer sufficient knowledge to start writing synthesisable VHDL upon successful completion of the course. We also provide additional VHDL training classes which cover the more advanced language constructs and methodologies.

Course benefits:

• Provides a complete understanding of the basic concepts in VHDL
• Introduces you to the syntax and language building blocks based on a number of common circuit elements
• Gives you practical experience of writing and verifying simple VHDL designs

For full course details and dates, please see the online VHDL training course schedule.

Intermediate VHDL (5-days online)

Ready for the next step? For those already familiar with VHDL (either through an introductory course or self-taught), this intermediate VHDL training course will broaden knowledge and enforce competency through application.

This instructor-led intermediate online VHDL training was designed to bridge the gap between possessing a basic working knowledge of VHDL and our Advanced VHDL Verification & Testbenches course. All our courses are delivered by time-served engineers whose experiences go far beyond just the theory.

Course benefits:

• Provides practical experience in writing, testing and synthesising VHDL code as well as how to implement it on an FPGA
• Enhances your current understanding of VHDL through problematic hardware coding issues
• Introduces you to transaction-based testbenches
• Introduces FSM coding techniques
• Provide VHDL hardware experience with an FPGA lab board

Each delegate will be provided with an FPGA development board which is used during the lab exercises and can be used after the course to further expand their VHDL knowledge.

For full course details and dates, please see the online VHDL training course schedule.

Advanced VHDL Testbenches & Verification

(10-days online) (5-days in-person)

Our Advanced in-person and online VHDL training course teaches the latest VHDL Verification techniques and methodologies for FPGAs and ASICs, including the Open Source VHDL Verification Methodology (OSVVM).

You will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog (UVM).

Unlike UVM, our methodology works with any simulator that supports VHDL-2008, removing the requirement to learn a new language or invest in new and costly tools.

Developed and delivered by Jim Lewis, chair of the IEEE VHDL standards working group and chief architect of OSVVM.

This training can either be delivered as one comprehensive course (Advanced VHDL Testbenches and Verification), or in two parts as detailed below:

Part 1: Essential VHDL Verification (6-days online) (3-days in-person)

You will learn to create structured transaction-based testbenches using either procedures or models (aka: verification IP or transaction level models). Both of these methods facilitate creation of simple, powerful, and readable tests.

Course benefits:

• Use OSVVM’s structure transaction base framework
• Write OSVVM Verification IP
• Simplify test writing using interface transactions (CpuRead, CpuWrite)
• Add error injection to interface transactions
• Implement a test plan that maximises reuse from RTL to core to system-level tests
• Write directed, algorithmic, constrained random, and Intelligent Coverage random tests
• Write Functional Coverage to track your test requirements (test plan)
• Simplify error reporting using OSVVM’s Alert and Affirm utilities
• Simplify conditional message printing (such as for debug) using OSVVM’s log utilities
• Add self-checking to tests
• Use OSVVM’s Generic Scoreboards and FIFOs
• Use OSVVM’s Synchronisation Utilities (WaitForBarrier, WaitForClock, …)
• Model analogue values and periodic waveforms
• Utilise OSVVM’s growing library of Open Source Verification IP

Part 2: Expert VHDL Verification (4-days online) (2-days in-person)

Building on the core topics covered in Essential VHDL Verification, Expert VHDL Verification teaches advanced topics including modeling multi-threaded models (such as AXI4-Lite), advanced functional coverage, advanced randomisation, creating data structures using protected types and access types, timing and execution, configurations and modeling RAM.

Course benefits:

• Write complex, multi-threaded verification components, such as AXI-Lite
• Use configurations to control which test runs
• Validate self-checking models
• Write AXI Stream Master and Slave Models
• Write models with interrupt handling capability
• Simplify memory model implementation using OSVVM’s MemoryPkg,
• Write protected types and access types
• Understand VHDL’s execution and timing
• Advanced Coverage and Randomisation techniques

For full course details and dates, please see the online and in-person VHDL training course schedule.

For all of the above courses, delegates will be provided with high quality materials including a lecture book and a detailed lab book (supporting all of the material covered during the course). For remote online courses, training materials and software licenses will be provided in advance of the course start date. The courses are split roughly 50/50 between lecture and lab time, so there is plenty of opportunity to reinforce the theory.

Online Live Course and In-Person Schedule