by Bernard Murphy
When I was at Atrenta, we always thought it would be great to do as-you-type RTL linting. It’s the natural use model for anyone used to writing text in virtually any modern application (especially on the Web, thanks to Google spell and grammar-checks). You may argue that you create your RTL in Vi or EMACS and you don’t need no stinking GUI. I have bad news for you – you are now officially part of the older generation. “Kids” graduating these days expect GUI support for any code they create. So get used to it.
Naturally there are limits to how far you can take real-time checking. It would be neither practical nor useful to launch CDC or formal analysis every time you hit the space or Return key. But that’s not what up and coming developers expect. They want the editor to flag and, if appropriate, correct the basic errors. This is especially important for VHDL development, which can be particularly challenging for VHDL novices (in which group I count myself). I should add that Sigasi provides similar capabilities for Verilog and for mixed-language.
On VHDL, you might argue “who cares – everything I do is in Verilog”. That purist stance is more difficult to sustain these days. Perhaps you have to integrate an Imagination Technologies GPU into your SoC (or one or more of many other IPs) and you need to add power management or other tweaks to support your integration. You’re going to have to deal with VHDL and the less experience you have, the more mistakes, you’re going to make (and the more time you’re going to spend trying to understand those mistakes). I can personally vouch for this. A language-aware editor would have made my life a lot easier.