Blog: OSVVM User Group meeting at DAC

OSVVM continues to develop through community feedback and deployment
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If you are performing constrained random verification and functional coverage in VHDL, you are likely already familiar with the Open Source VHDL Verification Methodology (OSVVM). If not, and you are considering broadening your verification methodology, head over to www.osvvm.org to find out more. You can also choose to learn directly from the author, Jim Lewis, about using OSVVM, and advanced VHDL verification in general, on our Advanced VHDL Testbenches & Verification workshop (see here for more details).

The first half  of 2015 has been a busy time in the OSVVM camp, with a couple of releases related to transcripts, alerts and logs that have delivered new functionality. These updates have provided functionality for different modules of your testbench: to write to a common transcript file (a formalised way to indicate test failures during simulation), as well as counting the number of such events and, finally, a method for conditionally printing messages from your code, complete with severity and verbosity control.

It will be interesting to see what else is in the pipeline for OSVVM during the rest of the year. Jim Lewis is the chief architect of OSVVM and regularly attends conferences throughout the year, as well as spending time with FirstEDA, delivering his Advanced VHDL Testbenches & Verification training across Europe. Jim will be holding a Birds of a Feather meeting at this year’s DAC conference in San Francisco, so if you would like to learn more about OSVVM and discuss its future directions, then why not pop along to Room 300 at 7pm on Tuesday 9^th June and get involved (assuming you’re fortunate enough to be making the trip!)