FPGAs have come an incredibly long way since their introduction in the mid-1980s. While low gate-count devices are still used extensively at one end of the spectrum we now have broad availability of multi-million gate FPGAs with embedded processor cores. Accordingly, the automation of design and verification tasks is essential if projects are to be completed on time and, importantly, with confidence.
Active-HDL is a Windows-based, integrated design creation and simulation solution for engineers working on projects ranging from simple PLD ‘glue logic’ all the way up to several-million-gate system-on-chip FPGAs.
ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.
Riviera-PRO addresses the verification requirements of engineers targeting large gate-count FPGAs, ASICs and System-on-Chip devices. It gives engineers the ultimate testbench in terms of productivity, reusability and automation; all by combining a high-performance simulation engine with advanced debugging capabilities (at different levels of abstraction).
Aldec and Microsemi have joined forces to offer an innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional One Time Programmable (OTP) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses flash-based, Microsemi ProASIC 3E FPGA technology for design prototype re-programmability.
StarVision PRO is an RTL-, gate- and SPICE-level integrated debugging and visualisation tool. It has been developed to help electronics engineers cope with the increasing use of building blocks in SoC designs, by allowing them to work at different design levels of abstraction (RTL, gate, transistor, analogue and parasitics) as well as with different design languages and netlist formats.
GateVision PRO is a graphical gate-level netlist analyser and netlist viewer. It provides designers working on even the largest ICs and SoCs with intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation.
360 DV-INSPECT increases the productivity of existing design and verification flows by adding push-button formal analysis; which can start as soon as the design under test (DUT) has been compiled, and independently of testbenches. In this way, critical bugs can be found much earlier than with a purely simulation-based flow.
360 DV-Verify is a unified coverage-driven assertion-based verification solution. The combination of a fully functional, high-performance formal property analyser with a unique assertion coverage evaluator eliminates the guesswork from quality assertion generation.
The Sigasi Studio platform was developed specifically to make HDL design easier and more efficient. It is based on the Eclipse platform and brings the same kind of real-time code checking assistance that software engineers have enjoyed for years firmly into the hardware arena.